Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the difficult factors in the continuing evolution toward smaller device size and higher density has been the ability to consistently form reliable integrated circuit wiring at smaller critical dimensions. For example, the reliability and electrical continuity of integrated circuitry wiring is determined by electrical continuity measurement methods following a manufacturing step, referred to as acceptance testing (WAT), to quickly determine and correct processing variables that may be causing circuitry defects.
Frequently, in order to determine processing variable that may lead to electrical continuity defects, it is desirable to form a test circuitry portion on a portion of the process wafer, referred to as a process control monitor (PCM), to determine the presence of defective circuitry portions. For example, the electrical integrity (continuity) of integrated circuitry is typically determined by passing an electrical signal through the process monitor control (PCM) circuitry.
One problem with prior art methods of electrical continuity WAT of PCM structures is that an uppermost metallization layer including a 2-dimensional circuit pattern is relied on for detecting circuitry defects in the most recently formed (uppermost) metallization layer. Frequently, testing of the most recently formed metallization layer is unable to detect the presence of defects in underlying metallization layers caused by formation of the most recently formed metallization layer.
For example, prior art metal continuity testing processes presently use 2-dimensional “snake shaped” metal line structures in testing of circuitry integrity in a metallization layer. If a circuitry defect is suspected in underlying metallization layers, frequently, the overlying layers must be removed to locate the defective area.
There is therefore a need in the semiconductor manufacturing art to develop an improved metrology method and integrated circuit monitoring structure to improve the identification and location of integrated circuit electrical continuity defects.
It is therefore an object of the invention to provide an improved metrology method and integrated circuit monitoring structure to improve the identification and location of integrated circuit electrical continuity defects, while overcoming other shortcomings of the prior art.